The present invention relates generally to a semiconductor device and, more particularly, to a semiconductor transistor device and a method of manufacturing the same.
Power transistors such as lateral (double) diffused metal-oxide-semiconductor (LDMOS) transistors and drain extension MOS (DEMOS) transistors are generally used in high-voltage applications. It is desirable that a power transistor is designed with a relatively high breakdown voltage and a relatively low on-resistance. However, high breakdown voltage and low on-resistance may be a trade-off for a power transistor. FIG. 1 is a layout of an LDMOS device 100 in prior art. Referring to FIG. 1, the LDMOS device 100 may include a high voltage n-type well (HVNW) region 101, a pair of n-type well regions 102 in the HVNW 101 and an n-type buried layer (NBL) 103 between the NW regions 102. The LDMOS 100 may be designed with a breakdown voltage (BV) of, for example, 60V (volts) for a 40V application. To reduce the on-resistance of the LDMOS device 100, an attempt to increase the concentration of the HVNW 101 may result in a decrease in the breakdown voltage, which may not be acceptable.
It may therefore be desirable to have a semiconductor device that has a relatively low on-resistance without compromise of the breakdown voltage.